1. Field of the Invention
The present invention relates, among microcomputers for data processing, specifically to a multi-CPU (MPU) system having a plurality of CPUs (Central Processing Unit) or MPUs (Microprocessor unit) mounted on a single chip, and particularly to a technique of testing sub CPUs (MPUs) thereof and a technique of constituting an emulation chip for the development of programs therefor.
2. Description of The Related Art
FIG. 1 through FIG. 4 schematically show an example of operation of a microcomputer program which is required to realize an environment for testing or debugging a multi-CPU system of the prior art.
The example of the prior art shown is a case of executing a program for the MN1880 series microcomputer made by Matsushita Electric Industrial Co., Ltd. The MN1880 series adopts a constitution wherein two sets of a CPU and a register are provided in the same memory space. File two CPUs will be called a CPU a and a CPU b, and FIG. 2 through FIG. 4 show schematic diagrams illustrative of the operation sequences of the CPU a and the CPU b in a time series.
FIG. 2 shows a state of the two CPUs executing instructions alternately. Specifically, as shown in the schematic diagram of FIG. 1, the program executed by the CPU a is constituted from a plurality of instructions IN1a, IN2a . . . IN16a and the program executed by the CPU b is constituted from a plurality of instructions IN1b, IN2b . . . IN16b. These instructions are stored in the same memory space with specific addresses being allocated thereto.
As shown in FIG. 2, these instructions are executed in such a sequence as the instruction IN1a of the CPU a is executed first, then the instruction IN1b of the CPU b is executed, followed by the execution of the instruction IN2a of the CPU a, the instruction IN2b of the CPU b, the instruction IN3a of the CPU a, the instruction IN3b of the CPU b, through the execution of the instruction IN16a of the CPU a and the instruction IN16b of the CPU b. Such a mode of operation by two CPUs to execute instructions alternately is called automatic swapping mode.
FIG. 3 and FIG. 4 show such an operation as the microcomputer switches the mode by executing a specific instruction thereby causing one of the CPUs to execute instructions continuously in a specified period of time. In FIG. 3, both CPUs are once reset thereby "WAITA=0, WAITB=0" is set to enter the automatic swapping mode, and the instructions are executed in the order of the instruction IN1a of the CPU a, IN1b of the CPU b, the instruction IN2a of the CPU a, IN2b of the CPU b, through the instruction IN5a of the CPU a and IN5b of the CPU b. At this point, the system exits the automatic swapping mode with "WAITB=1" being set to stop the CPU b, and thereafter instructions of the CPU a are executed in the order of IN6a, IN7a through IN10a.
In FIG. 4, both CPUs are once reset so that "WAITA=0, WAITB=0" is set to enter the automatic swapping mode, and the instructions IN1a of the CPU a and IN1b of the CPU b are executed. At this point, as the CPU a mode is requested, "WAITB=1" is set to stop the CPU b, and thereafter instructions of the CPU a are executed in the order of IN2a, IN3a through IN6a. Further, as CPU b mode is requested at this point, "WAITA=1, WAITB=0" is set to stop the CPU a, and thereafter instructions of the CPU b are executed in the order of IN2b, IN3b through IN6b. After this, the CPU a mode and the CPU b mode are alternately set similarly to the above, and some consecutive instructions of each CPU are executed alternately.
In such a system of the prior art, because two microcomputers operate in a time sharing scheme, there occurs no conflict in the access to the memory space. Therefore, when viewed from the memory space side, the two CPUs can make access to data stored in the memory at the respective timings without requiring the addition of a special control circuit. Thus when testing such a microcomputer, it is possible to test both CPUs by making access to bus signals which are activated in the time sharing scheme. Also with regard to the program developing environment, use of the same memory space enables it to emulate the two CPUs real-time simply by monitoring or controlling the memory space by means of an emulation controller.
However, although the example of the prior art described above is based on dual-CPU constitution, the two CPUs do not operate independently from each other concurrently, but are restricted to the time sharing operation. Thus the constitution has naturally a problem of limited speed of the CPU operation.
FIG. 5 through FIG. 10 show block diagrams of the constitution of a microcomputer H8/570 (microcomputer equipped with ISP) made by Hitachi Ltd., as another example of the prior art.
FIG. 5 through FIG. 8 are block diagrams illustrative of the overall constitution of the microcomputer H8/570 equipped with ISP wherein H8/500 is used as the main CPU and ISP blocks are provided in various peripheral function blocks. The ISP stands for intelligent Sub Processor, a kind of sub CPU wherein a plurality of functions can be programmed by built-in EPROM base. FIG. 9 and FIG. 10 are lock diagrams illustrative of the internal constitution of the ISP block. It is made in such a constitution that a program routine stored in a microprogram memory area which corresponds to a function No. specified by a programmable sequence generator (called SCM hereafter) is designated indirectly by means of an address register, so that the function defined by the program routine is executed.
The program of the ISP is a collection of short modules in principle, and provides a debugging environment by means of a software simulator, unlike the debugging environment of an ordinary microcomputer. A programmer checks each of the short modules having a single function, by means of the simulator to make sure that the module performs the desired function, and combines the modules according to a function table written in the SCM, thereby to achieve various functions. By writing the program which is completed as described above in the microprogram area comprising EPROM, SCM and address registers, the microcomputer which performs the intended functions is realized.
Because the ISP runs independently from and in parallel with the main CPU, use of the ISP makes it possible to perform highly real-time operation of the functions. However the concept of the ISP is programming through combination of simple functional modules, and therefore the ISP does not need the large scale program developing environment which is required by an ordinary microcomputer. For this reason, real-time debugging environment for the main CPU and the ISP is not provided in the microcomputer H8/570 which is equipped with the ISP.
As described above, a microcomputer of the conventional multi-CPU system wherein a plurality of CPUs are mounted on a chip has various limitations on providing special terminals for address bus, data bus and control bus exclusively for the sub CPU in order to facilitate testing of the microcomputer or program development for the sub CPU, because of the problem of chip layout, design problem of a multi-pin package, and other factors. Attempts of time sharing control through assignment of a plurality of functions to a terminal also encounter such limitations as the timing margin and problems such as complicated circuit, and therefore it has been very difficult to debug the target program by simultaneously operating a plurality of CPUs or MPUs mounted on a chip.